1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an LCD device and a method of driving the same, which can prevent vertical line noise from occurring due to a power ripple between a high-level voltage (VDD) and a low-level voltage (VSS) at a time for which a source driver IC charges/discharges a panel load.
2. Discussion of the Related Art
Generally, LCD devices adjust the light transmittance of liquid crystal with an electric field to display an image. To this end, the LCD devices include a panel in which a plurality of pixels are arranged in a matrix type, and a driving circuit for driving the panel.
In the panel, a plurality of gate lines and data lines are arranged to intersect, and the plurality of pixels are respectively formed in a plurality of areas prepared by respective intersection between the gate lines and the data lines.
The driving circuit includes a gate driver IC for driving the gate lines, a data driver IC for driving the data lines, and a timing controller for controlling the gate driver IC and the data driver IC. The gate driver IC sequentially supplies a scan signal (gate signal) to the gate lines, and thus sequentially drives the pixels of the panel in units of one line. The source driver IC supplies a plurality of pixel voltage signals to the respective data lines each time the gate signal is supplied to any one of the gate lines. The LCD devices may include at least one or more source driver ICs and at least one or more gate driver ICs.
FIGS. 1A and 1B are exemplary diagrams for describing a configuration and operation of a related art source driver IC. FIG. 1A illustrates a connection state between internal elements of the source driver IC, and FIG. 1B is a table for describing the switching operations of the elements of FIG. 1A. In FIG. 1B, a charge/share (C/S) mode is a mode using a charge share voltage. In the C/S mode, when a third switch SW3 is turned on, the panel is charged with the charge share voltage C/S. In FIG. 1B, a Hi-Z mode is a mode using no charge share voltage. In the Hi-Z mode, as shown in FIG. 1B, the third switch SW3 always maintains a turn-off state. Hereinafter, the related art will be described with the C/S mode as an example. FIG. 2 is a diagram showing waveforms of various signals in the related art source driver IC. FIG. 3 is an exemplary diagram showing output states of an internal clock and data in the related art source driver IC using an embedded point-to-point interface (EPI) type.
In the related art source driver IC, as shown in FIGS. 1A through 2, a first latch transfers data to a second latch at a rising time of a source output enable (SOE) signal, and, at a falling time of the SOE signal, the output of the source driver IC charges/discharges a panel load.
Specifically, when the SOE signal rises, a first switch SW1 is turned on, and thus, the first latch transfers data to the second latch, at which point the third switch SW3 is turned on and thus a panel is charged with a charge share voltage C/S. When the SOE signal falls, the first and third switches SW1 and SW3 are turned off and the second switch SW2 is turned on, and thus, image data are outputted from an output buffer (Amp) to the panel.
In a related art LCD devices, as described above, the first switch SW1 is turned on at a rising time of the SOE signal, and the second switch SW2 is turned on at a falling time of the SOE signal. Therefore, as shown in FIG. 2, the first switch SW1 is necessarily turned on after last image data, and thereafter, charge sharing is performed until the second switch SW2 is turned on from after the first switch SW1 is turned on. At a falling time of the SOE signal, when the second switch SW2 is turned on, data voltages are outputted from the source driver IC to the panel.
However, as shown in FIG. 2, an SOE falling time is a time at which the second switch SW2 is turned on and thus the source driver IC drives the panel load, and thus, a power ripple may occur between the high-level voltage VDD and the low-level voltage VSS.
Especially, a source driver IC using a timing controller and an EPI is greatly affected by a power ripple. In the source driver IC using the EPI, a delay lock loop (DLL) (which is included in the source driver IC) for generating an internal clock uses a low voltage. Therefore, as shown in FIG. 3, the above-described power ripple between the high-level voltage and the low-level voltage greatly affects the ground (GND) voltage VSS of a DLL circuit. In the DLL circuit, as shown in FIG. 3, the ripple of the ground (GND) voltage VSS shifts the phase of the internal clock. In this case, due to the shortage of a setup/hold time between data and a clock that are outputted from the source driver IC, noise (vertical line noise) occurs in a vertical line direction of the panel.
Even in a source driver IC using another interface (for example, mini-LVDS or the like) instead of the EPI as an interface between the timing controller and the source driver IC, circuits that are included in the source driver IC and use a low voltage may be affected by the above-described ripple, in which case noise may occur in a vertical line direction of the panel.
Moreover, even in circuits using no low voltage, the internal elements of a source driver IC may be affected by the above-described power ripple, in which case noise may occur in a vertical line direction of the panel.